Technical Field
The present invention relates generally to information processing and, in particular, to a bit line clamp voltage generator for Spin Torque Transfer (STT) Magnetoresistive Random Access Memory (MRAM) sensing.
Description of the Related Art
STT MRAM is an attractive emerging memory technology, offering non-volatility, high performance and high endurance. The STT MRAM memory cell typically includes a Magnetic Tunnel Junction (MTJ) in series with a Field Effect Transistor (FET) which is gated by the Word Line (WL). The Bit Line (BL) and Source Line (SL) run parallel to each other and perpendicular to the WL. The BL is connected to the MTJ and the SL is connected to the FET.
One cell along the BL is selected by turning on its WL. When a relatively large voltage is forced across the cell from BL to SL, the selected MTJ is written into a particular state. The written state is determined by the polarity of this voltage (BL high versus SL high).
When the cell is in the 0 or parallel state, the resistance of the MTJ is lower than when in the 1 or anti-parallel state. The selected cell is read by sensing the resistance from BL to SL. The sensing or read voltage must be much lower than the write voltage to avoid disturbing the cell. The state-dependent change in resistance is characterized by the parameter MR or magnetoresistance.
Many STT MRAM sensing techniques utilize a current sensing technique, in which an NFET, biased as a source follower, drives the sense amplifier (SA) input to the target read voltage. The resulting cell current is dropped through a PFET load device to produce a voltage which is detected by a comparator.
In these conventional STT MRAM sensing techniques, the generation of the gate voltage of the NFET source follower device (herein referred to as BLCLAMP) is critical to the operation of the sense amplifier, and presents considerable design challenges. If the BLCLAMP voltage is too large, the SA input voltage (Vsain) will be greater than the target, increasing the probability of read disturbs. If the BLCLAMP voltage is too small, the SA input voltage will be less than the target, reducing the magnitude of the signal and hence the read margin.
If BLCLAMP is a global reference, meaning that it is generated once per chip and distributed throughout the chip, the SA input voltage at each SA will depend strongly upon the NFET threshold voltage at each particular SA. In other words, Vsain will be dependent upon the long-range or cross-chip matching characteristics of the NFET device. Such long range matching characteristics are known to be quite poor and almost certainly result in an unacceptably wide distribution of the SA input voltage.
To avoid long-range device matching characteristics from affecting the SA input voltage, it is necessary to generate the BLCLAMP voltage locally, either for each individual SA or for a relatively small number of SAs which are in close proximity. However, if this is the case, then the circuit which generates BLCLAMP must be quite small and consume very little power, as many instances of the circuit will be required.
Conventional circuits for generating BLCLAMP are too large and draw too much current to be replicated many times per chip. The various feedback loops in these circuits imply a relatively long settling time for these circuits, implying that the circuits must be left on continuously, hence contributing to standby current. Additionally, the use of MTJs in the bias circuit may represent a reliability exposure, as these MTJs experience a much higher duty factor than the MTJs in the memory array.